module top_module(
    input clk,
    input reset,    // Synchronous reset to OFF
    input j,
    input k,
    output out); //  

    parameter OFF = 1'b0;
    parameter ON = 1'b1;
    
    reg state;
    
    always @(posedge clk) begin
        if(reset) begin
            state <= OFF;
        end
        else begin
            case(state)
                OFF:	if(j) begin
                    		state <= ON;
                		end
                		else begin
                            state <= state;
                        end
                ON:	if(k) begin
                    		state <= OFF;
                		end
                		else begin
                            state <= state;
                        end
            endcase
        end
    end
    
    assign out = state;

endmodule
